WEEK 7 Digital

ขั้นตอนดำเนินงานด้วย ISE 14.2

1.      New Project

2.      New Source

-- Coding architecture Behavioral of Encoder is begin           F <=   "0001" when (B='0' and A='0') else                      "0010" when (B='0' and A='1') else                      "0100" when (B='1' and A='0') else                      "1000" ;  end Behavioral;

Inplement All

3.      Assigned Pin

Inplement All

4.      Lode Program

Select file XXXX.jed Opertation à Program

แบบฝึกหัด

1.     ใช้ Xilinx ISE 14.4 ด้วยโปรแกรม VHDL ในการสร้าง 2 to 4 Line Encoder

library IEEE; use IEEE.STD_LOGIC_1164.ALL;   entity Encoder is     Port ( B : in  STD_LOGIC;            A : in  STD_LOGIC;            F : out  STD_LOGIC_VECTOR (3 downto 0)); end Encoder;   architecture Behavioral of Encoder is   begin         F <=    "0001" when (B='0' and A='0') else                 "0010" when (B='0' and A='1') else                 "0100" when (B='1' and A='0') else                 "1000" ;          end Behavioral;

2.       ใช้ Xilinx ISE 14.4 ด้วยโปรแกรม VHDL ในการสร้าง 7_Segment Encoder

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Encoder is Port ( Input : in STD_LOGIC_VECTOR (3 downto 0); F : out STD_LOGIC_VECTOR (6 downto 0)); end Encoder; architecture Behavioral of Encoder is begin F <= "1111110" when Input="0000" else "0110000" when Input="0001" else "1101101" when Input="0010" else "1111001" when Input="0011" else "0110011" when Input="0100" else "1011011" when Input="0101" else "1011111" when Input="0110" else "1110000" when Input="0111" else "1111111" when Input="1000" else "1111011" when Input="1001" else "1110111" when Input="1010" else "0011111" when Input="1011" else "1001110" when Input="1100" else "0111101" when Input="1101" else "1001111" when Input="1110" else "1000111" ; end Behavioral;

3.     จากโปรแกรมนับขึ้น 4 บิตด้วย VHDL ทดสอบกับ LED Logic Monitor 4 ดวง ให้ปรับปรุงโปรแกรมนี้เพื่อนับแบบเลข 8 บิต ทดสอบร่วมกับ 7_Segment Encoder ที่สร้างขึ้นจากข้อ 2 การแสดงผลจะเริ่มจาก 00 – FF

ขอบคุณวีดิโอจากคุณเพื่อนร่วมชั้น

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Counter is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; Outport : out STD_LOGIC_VECTOR (6 downto 0); Outport2 : out STD_LOGIC_VECTOR (6 downto 0)); end Counter; architecture Behavioral of Counter is signal pre_count: std_logic_vector(3 downto 0); signal pre_count2: std_logic_vector(3 downto 0); begin process(clk, reset) begin if reset = '1' then pre_count <= "0000"; elsif (clk='1' and clk'event) then pre_count <= pre_count + "1"; if pre_count = "1111" then pre_count2 <= pre_count2 + "1"; end if; end if; end process; Outport <= "1111110" when pre_count ="0000" else "0110000" when pre_count ="0001" else "1101101" when pre_count ="0010" else "1111001" when pre_count ="0011" else "0110011" when pre_count ="0100" else "1011011" when pre_count ="0101" else "1011111" when pre_count ="0110" else "1110000" when pre_count ="0111" else "1111111" when pre_count ="1000" else "1111011" when pre_count ="1001" else "1110111" when pre_count ="1010" else "0011111" when pre_count ="1011" else "1001110" when pre_count ="1100" else "0111101" when pre_count ="1101" else "1001111" when pre_count ="1110" else "1000111" ; Outport2 <= "1111110" when pre_count2 ="0000" else "0110000" when pre_count2 ="0001" else "1101101" when pre_count2 ="0010" else "1111001" when pre_count2 ="0011" else "0110011" when pre_count2 ="0100" else "1011011" when pre_count2 ="0101" else "1011111" when pre_count2 ="0110" else "1110000" when pre_count2 ="0111" else "1111111" when pre_count2 ="1000" else "1111011" when pre_count2 ="1001" else "1110111" when pre_count2 ="1010" else "0011111" when pre_count2 ="1011" else "1001110" when pre_count2 ="1100" else "0111101" when pre_count2 ="1101" else "1001111" when pre_count2 ="1110" else "1000111" ; end Behavioral;

4.     ปรับวงจรนับเป็น Up-Down Counter 4 bit โดยมี สัญญาญ CU ควบคุมการนับ ทดสอบร่วมกับ 7_Segment Encoder ที่สร้างขึ้นจากข้อ 2 การแสดงผลระหว่าง 0 - F

·        C ควบคุมการนับและหยุดนับ          ถ้าเป็น 1 ให้นับต่อ         ถ้าเป็น 0 ให้หยุดนับ

·        U ควบคุมทิศทางการนับ                 ถ้าเป็น 1 ให้นับขึ้น         ถ้าเป็น 0 ให้นับลง

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Counter is                                                 Port (                  Clk                                   : in  STD_LOGIC;                                                             Enable                            : in  STD_LOGIC;                                                             UpDown     : in  STD_LOGIC;                                                             Reset                              : in  STD_LOGIC;                                                             Output                           : out  STD_LOGIC_VECTOR (6 downto 0)); end Counter; architecture Behavioral of Counter is signal pre_count: std_logic_vector(3 downto 0); begin                                                 process(Clk, Reset, Enable, UpDown)                                                 begin                                                             if Reset = '1' then                                                                                           pre_count <= "0000";                                                             elsif (Clk='1' and Clk'event) then                                                                                           if Enable='1' then                                                                                                                         if UpDown='1' then                                                                                                                                                       pre_count <= pre_count + "1";                                                                                                                         else                                                                                                                                                       pre_count <= pre_count - "1";                                                                                                                         end if;                                                                                           end if;                                                             end if;                                                 end process;                                                  Output <=  "1111110" when pre_count ="0000" else                                                                                                                                                       "0110000" when pre_count ="0001" else                                                                                                                                                       "1101101" when pre_count ="0010" else                                                                                                                                                       "1111001" when pre_count ="0011" else                                                                                                                                                       "0110011" when pre_count ="0100" else                                                                                                                                                       "1011011" when pre_count ="0101" else                                                                                                                                                       "1011111" when pre_count ="0110" else                                                                                                                                                       "1110000" when pre_count ="0111" else                                                                                                                                                       "1111111" when pre_count ="1000" else                                                                                                                                                       "1111011" when pre_count ="1001" else                                                                                                                                                       "1110111" when pre_count ="1010" else                                                                                                                                                       "0011111" when pre_count ="1011" else                                                                                                                                                       "1001110" when pre_count ="1100" else                                                                                                                                                       "0111101" when pre_count ="1101" else                                                                                                                                                       "1001111" when pre_count ="1110" else                                                                                                                                                       "1000111" ; end Behavioral;

5.     ออกแบบ ALU(Arithmetic Logic Unit) โดยใช้ VHDL ให้มี Output F[3..0] และ Input A[1..0], B[1..0], C[2..0] กำหนดฟังก์ชันการทำงาน ดังนี้

C[2..0]	Logic Function		C[2..0]	Math Function
000	F=		100	F = A plus B
001	F = A OR B		101	F = A minus B
010	F = A AND B		110	F = -A
011	F = A XOR B		111	F = A plus 1

library IEEE; use IEEE.STD_LOGIC_1164.ALL; Use ieee.std_logic_unsigned.all; Use ieee.std_logic_arith.all; use IEEE.NUMERIC_STD.ALL; entity Sample5 is Port ( C : in STD_LOGIC_VECTOR (2 downto 0); iA : in STD_LOGIC_VECTOR (1 downto 0); iB : in STD_LOGIC_VECTOR (1 downto 0); F : out STD_LOGIC_VECTOR (3 downto 0)); end Sample5; architecture Behavioral of Sample5 is signal pre: std_logic_vector(3 downto 0); signal InA: std_logic_vector(3 downto 0); signal InB: std_logic_vector(3 downto 0); begin InA(1 downto 0) <= IA(1 downto 0); InB(1 downto 0) <= IB(1 downto 0); process(C,IA,IB) begin if(C="000") then pre <= not InA; elsif(C="001") then pre <= InA or InB; elsif(C="010") then pre <= InA and InB; elsif(C="011") then pre <= InA xor InB; elsif(C="100") then pre <= InA + InB; elsif(C="101") then pre <= InA - InB; elsif(C="110") then pre <= (not InA)+1; else pre <= InA + 1; end if ; end process; F <= pre; end Behavioral;